This invention relates to the implementation of a digital, programmable, spread spectrum clock generator that produces a clock signal with a defined lower spectral density for reduced electromagnetic interference with very low noise and jitter.
Today""s electronic products exhibit higher and higher performance as new, particularly digital, technology is brought to bear on both consumer and business problems. As the products become faster and more complex, the amount of radiated emissions in the form of electromagnetic interference (EMI) increases. Processors of one type or another are frequently a part of electronic appliances and equipment. Whether the processor is a microprocessor (xcexcP), a digital signal processor (DSP), or a microcontroller (xcexcC), each requires one or more clock signals for synchronization.
The performance of equipment using these processors is increasing very rapidly, and currently, state-of-the-art equipment like high-end personal computers (PCs) use processors with 200 MHz performance and above. For this type equipment, clock rates of 60-100 MHz are required. However, clock rates of xcexcPs in even the 30-40 MHz range are common today in digital electronic equipment.
In the United States, the Federal Communications Commission (FCC) sets and enforces maximum satisfactory EMI levels. These regulations are becoming even stricter with new requirements expected above 1 GHz. In Germany, the Verband Deutscher Elektrotechniker (VDE) sets EMI limits. The balance of the world follows the emission standards set by the Comite International Special Des Pertabations Radioelectriques (CISPR). It is necessary for the electronic equipment manufacturer to meet these standards, in order to be able to sell into markets governed by these bodies.
In order to comply with government limits on EMI emissions, several methods have been used to minimize EMI levels. Shielding, careful routing of signal traces, slowing clock rise and fall times and filtering are common ways of reducing the EMI of electronic equipment. However, each has problems of cost, space required and the engineering time involved.
xe2x80x9cSpread Spectrumxe2x80x9d (SS), crystal controlled oscillators have proven to be an effective solution for providing a reliable clock with reduced emissions for current and new high performance electronic equipment. The spread spectrum technique intentionally xe2x80x9cbroadbandsxe2x80x9d a signal which is normally narrow band, spreading the energy contained within the signal over a wider bandwidth. A frequency domain representation of a narrow band input clock signal without modulation and a xe2x80x9cspreadxe2x80x9d wide band output clock signal with modulation is shown in FIG. 1. See U.S. Pat. No. 5,491,458, entitled xe2x80x9cAPPARATUS FOR SPREADING THE SPECTRUM OF A SIGNAL AND METHOD THEREFOR,xe2x80x9d which issued on Feb. 13, 1996, for discussion of a phase modulator for spreading the spectrum of radiated emission of a clock signal.
Spread spectrum oscillators use a phase-locked-loop (PLL) technology to obtain wide deviation and crystal accuracy at frequencies as high as 135 MHz. Frequency modulation (FM) is used to spread the clock signal. For a discussion of this approach, see xe2x80x9cSpread Spectrum Clock Generation for the Reduction of Radiated Emissions,xe2x80x9d by Hardin, Feebler and Bush, pages 227-231, 1994 IEEE International Symposium on Electromagnetic Compatibility, Catalog # 94CH3347-2, ISDN 0-7803-1398-4. EMI is reduced at the center frequency by xe2x80x9cspreadingxe2x80x9d the bandwidth of the clock signal, effectively reducing the measured EMI at a given frequency. It should be noted that the total radiated energy, i.e., EMI, remains the same, but is xe2x80x9cspreadxe2x80x9d over a wider bandwidth than the original narrow band signal.
There are several ways to achieve spectral dispersion, or spread spectrum, of a signal. Both frequency and phase modulation are used. However, where low jitter is required, frequency modulation offers the preferred solution. For electronic equipment, there are two commonly used techniques that use frequency modulation for spread spectrum oscillators to reduce EMI without degrading the clock performance: 1) divider modulation, and 2) direct modulation of the voltage controlled oscillator (VOL.). Both techniques use a PLL and produce a frequency modulated clock.
Both of these techniques use PLLs which will be described only briefly herein, since they are well known to those in the art. The PLL is a circuit which synchronizes the output signal with reference to the input signal in frequency as well as phase. A more detailed description of the PLL can be found in xe2x80x9cThe Linear PLL,xe2x80x9d by Roland E. Best, Chapter 2, Phase-Locked Loops: Design, Simulation and Applications, McGraw-Hill, 3rd Edition, 1997.
A functional block diagram of a spread spectrum clock generator (SSCG) showing the two techniques mentioned above, for comparison
A functional block diagram of a spread spectrum clock generator (SSCG) showing the two techniques mentioned above, for comparison purposes, is shown in FIG. 2. Both techniques use a VOL. 13. In both techniques a clock input 10 is provided to an input of a phase detector (PD) 11. The output of the phase detector 11 is provided to a loop filter (F) 12. In the first technique the output of the loop filter 12 is provided to a VOL. 13. In the second technique, the output of the loop filter 12 is provided to a summer 14, the other input of the summer 14 being the output of a frequency modulator 15, which provides a varying voltage corresponding to the frequency modulation of the VOL. 13, with the output of the summer 14 being provided to the input to the VOL. 13. In both cases, the output of the VOL. 13 is the output of the SSCG and is provided to the input of a divider (DIV) 16, and the output of the divider 16 is provided to the other input of the phase detector 11. However, in the second technique, a frequency modulator 17 modulates the output frequency of the divider 16. The PD 11 compares the frequency and phase of the input clock waveform with the output waveform from the VOL. 13 and generates an error signal, in the form of a series of pulses indicating whether the feedback signal lags or leads the reference input signal, and having a width proportional to the phase difference between the two signals.
The F 12 then filters the unwanted harmonics from the PD error signal and integrates the voltage level of the input signal. The resulting output signal then goes to the VOL. 13 as a control voltage. The VOL. 13 control voltage is repeatedly adjusted with positive or negative signals until the output of the VOL. 13 is aligned with the input clock signal. The VOL. 13 is set to oscillate at a given frequency, depending on the output clock frequency required by the system. Where this frequency is greater than the input or reference frequency, the PLL 9 appears to multiply the frequency to the output. When this is the case, a divider is required in the feedback circuit from the VCO output to the PD in order to reduce the frequency back to that of the original input signal.
Thus, the two common prior art electronic techniques of modulating the signal to achieve a SSCG output from the PLL and the reduced emissions are 1) SSCG using PLL and Frequency Modulation and Summing of the VCO input signal, and 2) SSCG using PLL and Frequency Modulation of the Divider. A more detailed description of the first of these two techniques can be found in U.S. Pat. No. 5,488,627, entitled xe2x80x9cSPREAD SPECTRUM CLOCK GENERATOR AND ASSOCIATED METHOD,xe2x80x9d and which issued on Jan. 30, 1996. This technique is referred to hereinafter as the Direct Modulation of the VCO (DIR. MOD.) approach.
A more detailed description of the second of these two techniques can be found in an article entitled xe2x80x9cFrequency Modulation of System Clocks for EMI Reduction,xe2x80x9d by Cornelis D. Hoekstra, Article 13, pages 1-7, Hewlett-Packard Journal, August 1997. This technique is referred to hereinafter as the Divider Modulation (DIV. MOD.) approach.
For purposes of understanding the background of the present invention, it is useful to note that the DIR. MOD. method of producing the spread spectrum capacitively sums the modulation signal onto the input signal to the VCO. This method works well when the modulating frequency exceeds the natural loop PLL loop bandwidth by 2X. When the modulation frequency exceeds the PLL""s bandwidth by a large amount, the output frequency deviation (spectrum width) and can be approximated by:
F(deviation)=Kvxc3x97FFTERxc3x97VFMODxe2x80x83xe2x80x83(Equation 1)
where: Kv is the sensitivity of the VCO in Hz/v,
FTFER is the transfer function of the modulation port to the VCO input line in volt/volt, and
VFMOD is the modulating signal in volts.
If the modulation frequency is less than xc2xd the loop bandwidth, the loop will adjust and remove a large part of the applied modulation. Therefore, the desired peak deviation is reduced. Also, temperature, semiconductor manufacturing process and other variables will adversely affect the output. This is a serious drawback for this type of spread spectrum approach since SSCG designs typically use modulation frequencies in the range of 30 to 200 KHz. This range is inside the loop bandwidth of many PLLs included in complex LSI integrated circuits. Typical loop bandwiths of 1 MHz and higher are common for low phase noise integrated PLLs. The DIR. MOD. technique produces symmetrical modulation and is incapable of producing the unilateral FM necessary to maintain setup and hold margins in timing critical circuits. This limitation can be overcome by forcing an offset center frequency. However, in most cases this is not an option because of system requirements and the high cost of generating a unique frequency. This also tends to increase jitter.
The Divider Modulation (DIV. MOD.) approach modulates the divider in the PLL to get the desired spread spectrum. As an example, if the divider is originally set at N=10 and the input reference frequency is 1 MHz, the output frequency will be 10 MHz, as set in the VCO. If we then change the divider to 9, the frequency output will be 11.11 MHz. So, if we then modulate the divider back and forth between N=10 and N=9, with a 100 KHz square wave, the output of the PLL will cycle between 10 and 11.11 MHz at a 100 KHz rate. The spectrum produced is centered at 10.555 MHz and has a large number of sidebands spaced with a 100 KHz offset. The flexibility of this approach to select a desired frequency output is a problem. As can be seen, the modulation is limited between two integers i.e. 9 and 10 in this case. If alternate frequencies are specified that can not be obtained with the integers, an additional PLL may be required adding undesirable expense.
Frequently, a spread spectrum clock system will require an input clock frequency that is determined by a inexpensive crystal oscillator, and a specific spread spectrum output frequency that is not compatible or easily obtained by the DIV. MOD. approach. As an example, if the required spread spectrum clock output is 66 MHz with a 1 MHz input and a peak-to-peak frequency deviation of 4 MHz, there is no integer change of the PLL divider that can accomplish these requirements.
The DIV. MOD. approach can be thought of as a square wave modulation because the PLL is asked to jump instantaneously from one frequency to another. However, actual PLLs do not respond instantaneously. The frequency modulation waveform is consequently spectrally flatter than a square wave frequency modulation.
As is known, the cycle-to-cycle jitter has ranged from 0.5% to 2% in actual designs. This is too high for some systems. Therefore, triangle wave modulation, rather than square wave modulation, has been tried, with some success, in reducing the jitter.
The goal of a SSCG clock output is to approach 0% jitter. The less jitter that the SSCG approach has the more delay the designer can tolerate before reclocking the system. Even though jitter as low as 0.5% can be achieved with the DIV. MOD. approach, significant improvement is desirable as will be shown by this invention.
The present invention provides a digital spread spectrum clock generator. The generator includes a digital waveform generator adapted to generate a sequence of digital words representing a predetermined varying waveform, and an accumulator. The accumulator includes a first two input adder and a second two input adder, the second adder having its output stored and applied to a first input of the second adder. The first two input adder is adapted to receive at a first input a control word, to receive at a second input the sequence of digital words and to provide a sum output which is provided to a second input of the second adder. One of the bits of the output of the second adder is usable as a spread spectrum clock, or it may be provided to a phase locked loop to reduce jitter.
Thus, the present invention provides a digital programmable spread spectrum clock generator (SSCG) that produces a precise output waveform with a low spectral density for reduced EMI with very low noise or jitter. Additionally, the programmability allows for real-time precise, independent settings, or changes for the output center frequency, peak deviation and modulation frequency via software without changing hardware or software. As with many digital systems, some embodiments of this invention can operate over a wide temperature range of xe2x88x9240xc2x0 C. to +15xc2x0 C.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.